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PRELIMINARY
W228B
FTG for Integrated Core Logic with 133-MHz FSB
Features
* Maximized EMI suppression using Cypress's Spread Spectrum technology * Two copies of CPU clock at 66/100/133 MHz * Twelve copies of 100 MHz SDRAM clocks * One copy of PCI clock * One copy of APIC clock at 33 MHz, synchronous to CPU clock * Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video dot clock * Three copies of 3V 66-MHz fixed clock * One copy of 14.31818-MHz reference clock * Power down control * I2CTM interface for turning off unused clocks CPU, 3V66 Output Skew: ............................................175 ps PCI Output Skew: ........................................................500 ps CPU to SDRAM Skew (@ 133 MHz):.........................0.5 ns CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns PCI to APIC Skew: .....................................................0.5 ns Table 1. Pin Selectable Functions Tristate# 0 0 1 1 1 1 FSEL0 0 1 0 1 0 1 FSEL1 x x 0 0 1 1 CPU Three-state Test 66 MHz 100 MHz 133 MHz 133 MHz SDRAM Three-state Test 100 MHz 100 MHz 133 MHz 100 MHz
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter:................................................... 500 ps APIC, SDRAM Output Skew: ...................................... 250 ps
Block Diagram
VDDQ3
Pin Configuration [1]
APIC VDDQ2 GND REF0/FSEL1* VDDQ3 X1 X2 GND VDDQ3 3V66_0 3V66_1 3V66_AGP GND VDDQ3 PCI0_ICH PCI1 GND FSEL0 GNDA VDDA PWRDWN# SCLK SDATA GND VDDQ3 USB DOT Tristate# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 GND CPU0 CPU1 GND SDRAM0 SDRAM1 VDDQ3 GND SDRAM2 SDRAM3 SDRAM4 VDDQ3 GND SDRAM5 SDRAM6 VDDQ3 GND SDRAM7 SDRAM8 SDRAM9 VDDQ3 GND SDRAM10 SDRAM11 VDDQ3 GND SDRAM12
X1 X2
XTAL OSC
PLL REF FREQ
REF0/FSEL1
VDDQ2
SDATA SCLK
I2C Logic
Divider, Delay, and Phase Control Logic
2
CPU0:1
W228B
APIC VDDQ3
FSEL1:0 VDDA
PLL 1
2
3V66_0:1 3V66_AGP PCI0_ICH
Tristate#
PCI1 SDRAM0:12
13
PWRDWN# VDDQ3 VDDA
PLL2
USB DOT
Note: 1. Internal pull-down resistors present on input marked with *. Design should not solely rely on internal pull-down resister to set I/O pin LOW.
I2C is a trademark of Philips Corporation. Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Febuary 18, 2000, rev. *B
PRELIMINARY
Pin Definitions
Pin Name REF0/FSEL1 X1 X2 PCI0_ICH, PCI1 3V66_0:2, 3V66_AGP USB DOT Tristate#, FSEL0 PWRDWN# CPU0:1 Pin No. 4 6 7 15, 16 10, 11, 12 26 27 28, 18 21 54, 53 Pin Type I/O I O O O O O I I O Pin Description
W228B
Reference Clock: 3.3V 14.318-MHz clock output. This pin also serves as a strap option for CPU frequency selection. See Table 1 for detailed descriptions. Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Output: A connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PCI Clock 0 through 1: 3.3V 33-MHz PCI clock outputs. PCI1 can be individually turned off via I2C interface. 66-MHz Clock Output: 3.3V fixed 66-MHz clock. USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock output. Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal. Clock Function Selection pins: LVTTL-compatible input to select device functions. See Table 1 for detailed descriptions. Power-Down Control: LVTTL-compatible asynchronous input that places the device in power-down mode when held LOW. CPU Clock Outputs: Clock outputs for the host bus interface and integrated test port. Output frequencies run at 66 MHz, 100 MHz, or 133 MHz depending on the configuration of SEL0:1 and SEL133. Voltage swing set by VDDQ2. SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:12 can be individually turned off via I2C interface.
SDRAM0:12
51, 50, 47, 46, 45, 42, 41, 38, 37, 36, 33, 32, 29 1 23 22 5, 9, 14, 25, 31, 35, 40, 44, 49 20 2, 56 3, 8, 13, 17, 24, 30, 34, 39, 43, 48, 52, 55 19
O
APIC SDATA SCLK VDDQ3
O I/O I P
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the PCI clock outputs (33 MHz). Voltage swing set by VDDQ2. Data pin for I2C circuitry. Clock pin for I2C circuitry. 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane. Ground Connections: Connect all ground pins to the common system ground plane.
VDDA VDDQ2 GND
P P G
GNDA
G
2
PRELIMINARY
VDD
W228B
Output Strapping Resistor Series Termination Resistor Clock Load
10 k (Load Option 1) W228B Power-on Reset Timer Output Buffer Output Three-state
Q
Hold Output Low
D
10k (Load Option 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W228B is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel(R) architecture platform using graphics integrated core logic.
tor should be used. Figure 1 shows a suggested method for strapping resistor connections. After 2 ms, the pin becomes an output. Assuming the power supply has stabilized by then, the specified output frequency is delivered on the pins. If the power supply has not yet reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Pin Selectable Functions Table 2 outlines the device functions selectable through Tristate# and FSEL0:1. Specific outputs available at each pin are detailed in Table 2 below.
Functional Description
I/O Pin Operation REF0/FSEL1 is a dual-purpose l/O pin. Upon power-up the pin acts as a logic input for FSEL1 selection (see Table 1 and Table 2). If the pin is strapped to a HIGH state externally, CPU will be strapped LOW. CPU clock outputs will be determined by the status of SEL0:1 input pins. An external 10-k strapping resis-
Table 2. CK Whitney Truth Table Tristate# 0 0 1 1 1 1 FSEL0 0 1 0 1 0 1 FSEL1 X X 0 0 1 1 CPU Hi-Z TCLK/4 66 MHz 100 MHz 133 MHz 133 MHz SDRAM Hi-Z TCLK/4 100 MHz 100 MHz 133 MHz 100 MHz 3V66 Hi-Z TCLK/6 66 MHz 66 MHz 66 MHz 66 MHz PCI Hi-Z TCLK/12 33 MHz 33 MHz 33 MHz 33 MHz 48MHz Hi-Z TCLK/2 48 MHz 48 MHz 48 MHz 48 MHz REF Hi-Z TCLK 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz APIC Hi-Z TCLK/12 33 MHz 33 MHz 33 MHz 33 MHz Notes 2 4, 5 3, 6, 7 3, 6, 7 3, 6, 7 3, 6, 7
Notes: 2. Provided for board-level "bed of nails" testing. 3. "Normal" mode of operation. 4. TCLK is a test clock overdriven on the XTAL_IN input during test mode. 5. Required for DC output impedance verification. 6. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz. 7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
3
PRELIMINARY
Offsets Among Clock Signal Groups Figure 2 and Figure 3 represent the phase relationship among the different groups of clock outputs from W228B when it is providing a 66-MHz CPU clock and a 100-MHz CPU clock,
10 ns 20 ns
W228B
respectively. It should be noted that when the CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of phase with SDRAM clock outputs.
0 ns
30 ns
40 ns
CPU 66-MHz
Cycle Repeat
SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz
Figure 2. Group Offset Waveforms (66-MHz CPU/100-MHz SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100-MHz
Cycle Repeat
SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC 33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz
Figure 3. Group Offset Waveforms (100-MHz CPU/100-MHz SDRAM Clock)
4
PRELIMINARY
W228B
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC 33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz
Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100-MHz
Cycle Repeat
SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC 33-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz
Figure 5. Group Offset Waveforms (133-MHz CPU/133-MHz SDRAM Clock)
5
PRELIMINARY
Power Down Control
W228B
W228B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and all clock outputs are driven LOW.
0ns
25ns
50ns
75ns Center
1 VCO Internal CPU 100MHz 3V66 66MHz PCI 33MHz APIC 33MHz PwrDwn SDRAM 100MHz REF 14.318MHz USB 48MHz
2
Figure 6. W218 PWRDWN# Timing Diagram [8, 9, 10, 11] Table 3. W228B Maximum Allowed Current Max. 2.5V supply consumption Max. discrete cap loads, VDDQ2 = 2.625V All static inputs = VDDQ3 or VSS 10 mA 70 mA 100 mA TBD Max. 3.3V supply consumption Max. discrete cap loads VDDQ3 = 3.465V All static inputs = VDDQ3 or V SS 10 mA 280 mA 280 mA TBD
W228B Condition Powerdown Mode (PWRDWN# = 0) Full Active 66 MHz FSEL1:0 = 00 (PWRDWN# =1) Full Active 100 MHz FSEL1:0 = 01 (PWRDWN# =1) Full Active 133 MHz FSEL1:0 = 11 (PWRDWN# =1)
Notes: 8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition. 9. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W228B. 10. The shaded sections on the SDRAM, REF, and USB clocks indicate "don't care" states. 11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
6
PRELIMINARY
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 7. As shown in Figure 7, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F)
W228B
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 8. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is -0.5% of the selected frequency. Figure 8 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate value for bit 3 in data byte 0 of the I2C data stream. Refer to page 9 for more details.
EMI Reduction
Spread Spectrum Enabled
NonSpread Spectrum
Figure 7. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN.
Figure 8. Typical Modulation Profile
7
100%
PRELIMINARY
1 bit Start bit 7 bits Slave Address 1 R/W 1 Ack 8 bits Command Code 1 Ack
W228B
Byte Count = N
Ack 1 bit
Data Byte 1 8 bits
Ack 1
Data Byte 2 8 bits
Ack 1
...
Data Byte N 8 bits
Ack 1
Stop 1
Figure 9. An Example of a Block Write[12] Serial Data Interface The W228B features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. A block write begins with a slave address and a write condition. After the command code the core logic issues a byte count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transTable 4. Example of Possible Byte Count Value Byte Count Byte MSB 0000 0000 0000 0000 0000 0000 0000 0000 0010 LSB 0000 0001 0010 0011 0100 0101 0110 0111 0000 Not allowed. Must have at least one byte. Data for functional and frequency select register (currently byte 0 in spec) Reads first two bytes of data (byte 0 then byte1) Reads first three bytes (byte 0, 1, 2 in order) Reads first four bytes (byte 0, 1, 2, 3 in order) Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[13] Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[13] Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) Max. byte count supported = 32 Notes fer a maximum of 32 data bytes. The slave receiver address for W228B is 11010010. Figure 9 shows an example of a block write. The command code and the byte count bytes are required as the first two bytes of any transfer. W228B expects a command code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. Table 4 shows an example of a possible byte count value. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W228B. However, these bytes must be included in the data write sequence to maintain proper byte allocation.
Table 5. Serial Data Interface Control Functions Summary Control Function Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Enables or disables spread spectrum clocking. Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For EMI reduction.
Spread Spectrum Enabling (Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be written as 0. duction device testing.
Notes: 12. The acknowledgment bit is returned by the slave/receiver (W228B). 13. Data Bytes 3 to 7 are reserved.
8
PRELIMINARY
W228B Serial Configuration Map
1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register (1 = Enable, 0 = Disable)[14] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 27 26 -Reserved Reserved Reserved Reserved Spread Spectrum (1 = On/0 = Off) DOT USB Reserved Name Reserved Reserved Reserved Reserved (Disabled/Enabled) (Active/Inactive) (Active/Inactive) Reserved Pin Description
W228B
2. All unused register bits (reserved and N/A) should be written to a "0" level. 3. All register bits labeled "Initialize to 0" must be written to zero during initialization. Failure to do so may result in higher than normal operating current. 4. Only Byte 0, 1, and 2 are defined in W228B. Byte 3 to Byte 7 are reserved and must be written to "zero."
Byte 1: Control Register (1 = Enable, 0 = Disable)[14] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 38 41 42 45 46 47 50 51 SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Name (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description
Byte 2: Control Register (1 = Enable, 0 = Disable)[14] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 12 29 32 33 36 37 16 3V66_AGP SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8 PCI1 (Reserved) Name (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Reserved) Pin Description
Note: 14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation.
9
PRELIMINARY
Byte 3: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# Name Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' SDRAM 133-MHz Mode Enable Default is Disabled = '0', Enabled = '1' Pin Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Disabled/Enabled)
W228B
Byte 4: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# Name Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Reserved Drive to '0' Pin Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
10
PRELIMINARY
DC Electrical Characteristics
Absolute Maximum DC Power Supply Parameter VDD3 VDDQ2 VDDQ3 TS Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage 3.3V Supply Voltage Storage Temperature Min. -0.5 -0.5 -0.5 -65 Max. 4.6 3.6 4.6 150
W228B
Unit V V V C
Absolute Maximum DC I/O Parameter Vih3 Vil3 ESD prot. Description 3.3V Input High Voltage 3.3V Input Low Voltage Input ESD Protection Min. -0.5 -0.5 2000 Max. 4.6 Unit V V V
DC Operating Requirements Parameter VDD3 VDDQ3 VDDQ2 VDD3 = 3.3V5% Vih3 Vil3 Iil VDDQ2 = 2.5V5% Voh2 Vol2 VDDQ3 = 3.3V5% Voh3 Vol3 VDDQ3 = 3.3V5% Vpoh3 Vpol3 Cin Cxtal Cout Lpin PCI Bus Output High Voltage PCI Bus Output Low Voltage Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance 0 0 13.5 Ioh=(-1 mA) Iol=(1 mA) 2.4 0.55 5 22.5 6 7 70 V V pF pF pF nH C 3.3V Output High Voltage 3.3V Output Low Voltage Ioh=(-1 mA) Iol=(1 mA) 2.4 0.4 V V 2.5V Output High Voltage 2.5V Output Low Voltage Ioh=(-1 mA) Iol=(1 mA) 2.0 0.4 V V 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current[15] 0Ambient Temperature No Airflow Ta Note: 15. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
11
PRELIMINARY
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, V DDQ2= 2.5V5% fXTL = 14.31818 MHz Spread Spectrum function turned off
W228B
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[16] AC Electrical Characteristics 66.6-MHz Host Parameter TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL Description Host/CPUCLK Period Host/CPUCLK High Time Host/CPUCLK Low Time Host/CPUCLK Rise Time Host/CPUCLK Fall Time SDRAM CLK Period (100-MHz) SDRAM CLK High Time (100-MHz) SDRAM CLK Low Time (100-MHz) SDRAM CLK Rise Time (100-MHz) SDRAM CLK Fall Time (100-MHz) SDRAM CLK Period (133-MHz) SDRAM CLK High Time (133-MHz) SDRAM CLK Low Time (133-MHz) SDRAM CLK Rise Time (133-MHz) SDRAM CLK Fall Time (133-MHz) APIC 33-MHz CLK Period APIC 33-MHz CLK High Time APIC 33-MHz CLK Low Time APIC CLK Rise Time APIC CLK Fall Time 3V66 CLK Period 3V66 CLK High Time 3V66 CLK Low Time 3V66 CLK Rise Time 3V66 CLK Fall Time PCI CLK Period PCI CLK High Time PCI CLK Low Time PCI CLK Rise Time PCI CLK Fall Time Min. 15.0 5.2 5.0 0.4 0.4 10.0 3.0 2.8 0.4 0.4 7.5 1.87 1.67 0.4 0.4 30.0 12.0 12.0 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 Max. 15.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 8.0 N/A N/A 1.6 1.6 N/A N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 100-MHz Host Min. 10.0 3.0 2.8 0.4 0.4 10.0 3.0 2.8 0.4 0.4 7.5 1.87 1.67 0.4 0.4 30.0 12.0 12.0 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 Max. 10.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 8.0 N/A N/A 1.6 1.6 N/A N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 133-MHz Host Min. 7.5 1.87 1.67 0.4 0.4 10.0 3.0 2.8 0.4 0.4 7.5 1.87 1.67 0.4 .04 30.0 12.0 12.0 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 Max. 8.0 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 8.0 N/A N/A 1.6 1.6 N/A N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16, 17 19 20 16, 18 19 20 16 19 20 16 19 20 16 19 20 Notes 16 19 20
Notes: 16. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks. 17. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs. 18. TLOW is measured at 0.4V for all outputs. 19. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specification. 20. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.
12
PRELIMINARY
AC Electrical Characteristics (continued) 66.6-MHz Host Parameter tpZL, tpZH tpLZ, tpZH tstable Description Output Enable Delay (All outputs) Output Disable Delay (All outputs) All Clock Stabilization from Power-Up Min. 1.0 1.0 Max. 10.0 10.0 3 100-MHz Host Min. 1.0 1.0 Max. 10.0 10.0 3 133-MHz Host Min. 1.0 1.0 Max. 10.0 10.0 3
W228B
Unit ns ns ms
Notes
Group Skew and Jitter Limits Output Group CPU SDRAM APIC 48MHz 3V66 PCI REF Pin-Pin Skew Max. 175 ps 250 ps 250 ps 250 ps 175 ps 500 ps N/A Cycle-Cycle Jitter 250 ps 250 ps 500 ps 500 ps 500 ps 500 ps 1000 ps Duty Cycle 45/55 45/55 45/55 45/55 45/55 45/55 45/55 Nom Vdd 2.5V 3.3V 2.5V 3.3V 3.3V 3.3V 3.3V Skew, Jitter Measure Point 1.25V 1.5V 1.25V 1.5V 1.5V 1.5V 1.5V
Output Buffer Clock Output Wave
Test Point
Test Load TPERIOD Duty Cycle THIGH
2.0
2.5V Clocking Interface
1.25 0.4
TLOW TRISE TFALL TPERIOD Duty Cycle THIGH
2.4
3.3V Clocking Interface
1.5 0.4
TLOW TRISE TFALL
Figure 10. Output Buffer
Ordering Information
Ordering Code W228B Document #: 38-00883-B Package Name H Package Type 56-pin SSOP (300 mils)
13
PRELIMINARY
Layout Diagram
+3.3V Supply FB
VDDQ3
W228B
+2.5V Supply FB
VDDQ2
10 F
C4
0.005 F
C3
C1
10 F
0.005 F
C2
G
G
G
G G
G
G
C2
G
1 2 3 4 5 6 7 8 9
10
G
V V
G
G
G
V
G
G G
V
G
V
G
G
G
VDDQ3
5
C5 G
G C6
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
G G
V
G
V
G
G
V
G
G
V
G
Core G
V
G G PLL2
V
G
G
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
C5 = 47 F
G C1
G
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) C1 & C3 = 10-22 F C2 & C4 = 0.005 F C6 = 0.1 F
W228B
14
G
G
G
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors All VDD Bypass = 0.1 F
PRELIMINARY
Package Diagram
56-Pin Shrink Small Outline Package (SSOP, 300 mils)
W228B
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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